3D TSV Test Approaches : Outlook for 2014
Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of the TSVs. There are ideas about how to perform 3D TSV test with top side contact during standard wafer probe. For example, Giorgio di Natale is proposing to test TSVs by analyzing their RC behavior, which can be done by top side contact and adequate built-in self test (BIST) on the silicon. But all methods are finally incomplete tests, as, for example, defects that are very close to the inner end of the TSVs cannot be detected.
In this 3DInCires blog post Bernhard Lorenz, VP Engineering of Multitest, looked at various approaches that are currently implemented in the industry.